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HY514400B
FUNCTIONAL BLOCK DIAGRAM
DQ0 ~ DQ3
4
8 OE
Data Input Buffer
Data Output Buffer
WE CAS
4
4
CAS Clock Generator 4 A0 A1 A2 Address Buffer A3 A4 A5 A6 A7 A8 A9 Row Predecoder (10) 10 Refresh Controller Sense Amp I/O Gate Cloumn Predecoder (10) 10 Column Decoder
Refresh Counter (10)
Row Decoder
Memory Array 1,048,576 x 4
RAS
RAS Clock Generator
Substrate Bias Generator
VCC VSS
1Mx4,FP DRAM Rev.10 / Jan.97
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HY514400B
PIN CONFIGURATION (Marking Side)
DQ0 DQ1 WE RAS A9
1 2 3 4 5
26 25 24 23 22
VSS DQ3 DQ2 CAS OE
DQ0 DQ1 WE RAS A9
1 2 3 4 5
26 25 24 23 22
VSS DQ3 DQ2 CAS OE
A0 A1 A2 A3 Vcc
9 10 11 12 13
18 17 16 15 14
A8 A7 A6 A5 A4
A0 A1 A2 A3 Vcc
9 10 11 12 13
18 17 16 15 14
A8 A7 A6 A5 A4
20/26 Pin Plastic SOJ (300mil)
20/26 Pin Plastic TSOP- II (300mil)
PIN DESCRIPTION
Pin Name /RAS /CAS /WE /OE A0~A9 DQ0~DQ3 Vcc Vss Parameter Row Address Strobe Column Address Strobe Write Enable Output Enable Address Input Data In/Out Power (5V) Ground
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HY514400B
ABSOLUTE MAXIMUM RATINGS
Symbol TA TSTG VIN, VOUT VCC IOS PD TSOLDER Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VCC relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature Y Time Rating 0 to 70 -55 to 150 -1.0 to 7.0 -1.0 to 7.0 50 0.9 260 Y 10 Unit C C V V mA W C Y sec
Note : Operation at or above Absolute Maximum Ratings can adversely affect device reliability
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0C to 70C ) Symbol VCC VIH VIL Parameter Power Supply Voltage Input High Voltage Input Low Voltage Min 4.5 2.4 -1.0 Typ 5.0 Max 5.5 VCC+1.0 0.8 UNIT V V V
Note : All voltages are referenced to VSS.
DC OPERATING CHARACTERISTICS
Symbol ILI ILO Parameter Input Leakage Current (Any input) Output Leakage Current (Any input) Output Low Voltage Output High Voltage Test condition VSS VIN VCC + 1.0 All other pins not under test = VSS VSS VOUT VCC /RAS & /CAS at VIH IOL = 4.2mA IOH = -5.0mA Min -10 -10 2.4 Max 10 10 0.4 Unit A A V V
VOL VOH
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HY514400B
DC CHARACTERISTICS
(TA = 0C to 70C , VCC = 5V 10%, VSS = 0V, unless otherwise noted.) Symbol ICC1 Parameter Operating Current Test condition /RAS, /CAS Cycling tRC = tRC(min) /RAS, /CAS VIH(min) Other inputs VSS 50 60 70 50 60 70 Speed 50 60 70 Max. 100 90 80 2 Unit
mA
ICC2
TTL Standby Current
mA
ICC3
/RAS-only Refresh Current
/RAS Cycling,/CAS = VIH tRC = tRC(min)
100 90 80 70 60 50 1 200 100 90 80
mA
ICC4
Fast Page mode Current
/CAS Cycling, /RAS = VIL tHPC = tHPC(min) /RAS = /CAS VCC - 0.2V /RAS & /CAS = 0.2V tRC = tRC(min.) tRC=125s /CAS = CBR cycling or 0.2V /OE & /WE = VCC - 0.2V Address = Vcc-0.2V or 0.2V DQ0~DQ3 = Vcc-0.2, 0.2V or Open /RAS & /CAS = 0.2V Other pins are same as ICC7
mA mA A mA
ICC5
CMOS Standby Current /CAS-before-/RAS Refresh Current Battery Back-up Current (SL-part)
SL-part 50 60 70
ICC6
ICC7
300
A
ICC8
Self Refresh Current (SL-part)
200
A
Note 1. ICC1, ICC3, ICC4 and ICC6 depend on output loading and cycle rates(tRC and tPC). 2. Specified values are obtained with output unloaded. 3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4, address can be changed maximum once while /CAS=VIH within one cycle time tPC. 4. Only tRAS(max) = 1s is applied to refresh of battery backup but tRAS(max) = 10s is to applied to normal functional operation. 5. Icc5(max.), Icc7 and Icc8 are applied to SL-part only.
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HY514400B
AC CHARACTERISTICS
(TA = 0 C to 70 C, VCC = 5V 10% , VSS = 0V, unless otherwise noted.) 50ns Symbol tRC tRWC tPC tPRWC tRAC tCAC tAA tCPA tCLZ tT tRP tRAS tRASP tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL Parameter Min Random read or write cycle time Read-modify-write cycle time Fast Page mode cycle time Fast Page mode read-modify-write cycle time Access time from /RAS Access time from /CAS Access time from column address Access time from /CAS precharge /CAS to output low impedance Transition time(rise and fall) /RAS precharge time /RAS pulse width /RAS pulse width(FP mode) /RAS hold time /CAS hold time /CAS pulse width /RAS to /CAS delay time /RAS to column address delay time /CAS to /RAS precharge time /CAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address hold time from /CAS Column address to /RAS lead time Read command set-up time Read command hold time referenced to /CAS Read command hold time referenced to /RAS Write command hold time Write command hold time from /RAS Write command pulse width Write command to /RAS lead time 90 130 35 75 0 3 30 50 50 15 50 15 15 10 5 10 0 8 0 15 40 25 0 0 0 10 40 10 15 Max 50 15 25 30 50 10K 200K 10K 35 25 Min 110 155 40 80 0 3 40 60 60 15 60 15 20 15 5 10 0 10 0 15 50 30 0 0 0 10 45 10 15 Max 60 15 30 35 50 10K 200K 10K 45 30 Min 130 185 45 95 0 3 50 70 70 20 70 20 20 15 5 10 0 10 0 15 55 35 0 0 0 15 55 15 20 Max 70 20 35 40 50 10K 200K 10K 50 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 14 6,14 6 14 14 14 9 10 15 17 4,9,10 4,9 4,10 4,15 4 3 60ns 70ns Unit Note
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HY514400B
AC CHARACTERISTICS
Continued 50ns Symbol tCWL tDS tDH tDHR tREF Refresh period(SL-part) tWCS tCWD tRWD tAWD tCSR tCHR tRPC tCPT tROH tOEA tOED tOEZ tOEH tCPWD tRHCP tRASS tRPS tCHS tWRP tWRH tWTS tWTH Write command set-up time /CAS to /WE delay time /RAS to /WE delay time Column address to /WE delay time /CAS set-up time(CBR cycle) /CAS hold time(CBR cycle) /RAS to /CAS precharge time /CAS precharge time(CBR counter test) /RAS hold time referenced to /OE /OE access time /OE to data delay Output buffer turn-off delay time from /OE /OE command hold time /WE delay time from /CAS precharge /RAS hold time from /CAS precharge /RAS pulse width(self refresh) /RAS Precharge Time (Self refresh) /CAS Hold Time (Self refresh) /WE to /RAS Precharge time (CBR cycle) /WE to /RAS Hold time (CBR cycle) Write Command Set-up time (Test Mode In) Write Command Hole time (test Mode In) 128 0 35 70 45 5 10 5 20 10 15 0 15 50 30 100 120 -50 10 10 10 10 15 15 128 0 40 85 55 5 10 5 20 10 15 0 15 55 35 100 130 -50 10 10 10 10 15 15 128 0 50 100 65 5 10 5 25 10 20 0 20 65 40 100 150 -50 10 10 10 10 20 20 ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 5 Parameter Min Write command to /CAS lead time Data-in set-up time Data-in hold time Data-in hold time Referenced to /RAS Refresh period(1024 cycles) 15 0 15 40 16 Max Min 15 0 15 45 16 Max Min 20 0 15 55 16 Max ns ns ns ns ms 12 11 84 8 8 8 14 15 14 17 16 7 7 60ns 70ns Unit Note
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HY514400B
NOTE
1. An initial pause of 200s is required after power-up followed by 8 /RAS only refresh cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CBR refresh cycles instead of 8 /RAS-only refresh cycles are required. 2. If /RAS=Vss during power-up,the HY514400B could begin an active cycle. This condition results in higher current than necessary current which is demanded from the power supply during power-up. It is recommended that /RAS and /CAS track with Vcc during power-up or be held at a valid VIH in other to minimize the power-up current. 3. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min.) and VIL(max.),and are assumed to be 5ns for all inputs. 4. Measured at VOH=2.0V and VOL=0.8V with a load equivalent to 2TTL loads and 100pF. 5. tOFF(max.) and tOEZ define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 6. Either tRCH or tRRH must be satisfied for a read cycle. 7. tCEZ and tOEZ define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 8. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS(min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. If tRWD tRWD(min.), tCWD tCWD(min.), tAWD tAWD(min), and tCPWD tCPWD(min.), the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 9. Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC. 10.Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA. 11.tREF(max.)=128ms is applied to SL-parts only. 12.A burst of 1024 CBR refresh cycles must be executed within 16ms (128ms for SL-part) after exiting self refresh. 13.When CAS goes low at the same time, 4bits data are written into the device. 14.These parameters are determined by the earlier falling edge of /CAS. 15.These parameters are determined by the later rising edge of /CAS. 16.tCWL must be satisfied by /CAS for 4bits access cycle. 17.tCP and tCPT are measured when /CAS and is high state.
CAPACITANCE
(TA = 25C, VCC = 5V 10%, VSS = 0V and f=1MHz, unless otherwise noted.) Symbol CIN1 CIN2 CDQ Parameter Input Capacitance (A0~A9) Input Capacitance (/RAS, /CAS, /WE, /OE) Data Input / Output Capacitance (DQ0~DQ3) Typ. Max 5 7 7 Unit pF pF pF
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